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PD60364
IR3840MPBF
SupIRBuck
Features
* * * * * * * * * * * * * * * * * * *
TM
HIGHLY EFFICIENT
Description
The IR3840 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC synchronous Buck regulator. The MOSFETs copackaged with the on-chip PWM controller make IR3840 a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3840 is a versatile regulator which offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. The switching frequency is programmable from 250kHz to 1.5MHz for an optimum solution. It also features important protection functions, such as Pre-Bias startup, hiccup current limit and thermal shutdown to give required system level security in the event of fault conditions.
INTEGRATED 12A SYNCHRONOUS BUCK REGULATOR
Greater than 96% Maximum Efficiency Wide Input Voltage Range 1.5V to 16V Wide Output Voltage Range 0.7V to 0.9*Vin Continuous 12A Load Capability Integrated Bootstrap-diode High Bandwidth E/A for excellent transient performance Programmable Switching Frequency up to 1.5MHz Programmable Over Current Protection (Hiccup) PGood output Precision Reference Voltage (0.7V, +/-1%) Programmable Soft-Start Enable Input with Voltage Monitoring Capability Enhanced Pre-Bias Start-up Seq input for Tracking applications -40oC to 125oC operating junction temperature Thermal Protection Pin compatible option for 4A and 8A devices 5mm x 6mm Power QFN package, 0.9 mm height Lead-free, halogen-free and RoHS compliant
Applications
* * * * Server Applications Storage Applications Embedded Telecom Systems Distributed Point of Load Power Architectures
1.5V * * *
Netcom Applications Computing Peripheral Voltage Regulators General DC-DC Converters
4.5V Seq Vcc PGood PGood
Enable
Vin
Boot Vo SW
OCSet Fb
Rt Comp
SS/ SD
Gnd
PGnd
Fig. 1. Typical application diagram 06/18/09 1
IR3840MPBF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
* * * * * * * * * * * *
Vin ............................................................. -0.3V to 25V Vcc ............................................................... -0.3V to 8V (Note2) Boot SW .......................................................... -0.3V to 33V ........................................................... -0.3V to 25V(DC), -4V to 25V(AC, 100ns) .................................................... -0.3V to Vcc+0.3V (Note1)
Boot to SW OCSet
........................................................ -0.3V to 30V, 30mA ...................................... ... -0.3V to Vcc+0.3V (Note1)
Input / output Pins
PGND to GND .................................................. -0.3V to +0.3V Storage Temperature Range ................................... -55C To 150C Junction Temperature Range ................................... -40C To 150C (Note2) ESD Classification ................................. ......... JEDEC Class 1C Moisture sensitivity level.......................................JEDEC Level 3@260 C
Note1: Must not exceed 8V Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
5mm x 6mm POWER QFN
SW
VIN
12
11
10
PGnd
JA = 35 o C / W J -PCB = 2 o C / W
Boot Enable
13 14 1 2 3
15
Gnd
9 8
VCC PGood
4
5
6
7
ORDERING INFORMATION PACKAGE DESIGNATOR M M 06/18/09
Seq
FB COMP Gnd Rt
SS OCSet
PACKAGE DESCRIPTION IR3840MTRPbF IR3840MTR1PbF
PIN COUNT 15 15
PARTS PER REEL 4000 750 2
IR3840MPBF
Block Diagram
Fig. 2. Simplified block diagram of the IR3840
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Pin Description
Pin
1 2 3 4 5
Name
Seq Fb Comp Gnd Rt
Description
Sequence pin. Use two external resistors to set Simultaneous Power up sequencing. If this pin is not used connect to Vcc. Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to provide loop compensation. Signal ground for internal reference and control circuitry. Set the switching frequency. Connect an external resistor from this pin to Gnd to set the switching frequency. Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to Gnd to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. Current limit set point. A resistor from this pin to SW pin will set the current limit threshold. Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to Vcc. If unused, it can be left open. This pin powers the internal IC and the drivers. A minimum of 1uF high frequency capacitor must be connected from this pin to the power ground (PGnd). Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system's power ground plane. Switch node. This pin is connected to the output inductor.
6
SS/SD
7 8 9 10 11
OCSet PGood VCC PGnd SW VIN Boot Enable Gnd
12 13 14 15
Input voltage connection pin. Supply voltage for high side driver. A 0.1uF capacitor must be connected from this pin to SW. Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Enable section). Connect this pin to Vcc if it is not used. Signal ground for internal reference and control circuitry.
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Recommended Operating Conditions
Symbol
Vin Vcc Boot to SW Vo Io Fs Tj
Definition
Input Voltage Supply Voltage Supply Voltage Output Voltage Output Current Switching Frequency Junction Temperature
Min
1.5 4.5 4.5 0.7 0 225 -40
Max
16 5.5 5.5 0.9*Vin 12 1650 125
Units
V A kHz o C
Electrical Specifications
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oCParameter Power Loss
Power Loss Ploss Vcc=5V, Vin=12V, Vo=1.8V, Io=12A, Fs=600kHz, L=0.6uH, Note4 2.6 W
Symbol
Test Condition
Min
TYP
MAX
Units
MOSFET Rds(on)
Top Switch Bottom Switch Rds(on)_Top Rds(on)_Bot
VBoot -Vsw =5V, ID=14A, Tj=25 C Vcc=5V, ID=14A, Tj=25 C
0 0
8.3 5.9
12.0 8.0 m
Reference Voltage
Feedback Voltage Accuracy VFB 0 Co o o o
0.7 -1.0 -2.0 +1.0
V % +2.0
Supply Current
Vcc Supply Current (Standby) Vcc Supply Current (Dyn) ICC(Standby) ICC(Dyn) SS=0V, No Switching, Enable low SS=3V, Vcc=5V, Fs=500kHz Enable high 15 500 uA mA
Under Voltage Lockout
Vcc-Start-Threshold Vcc-Stop-Threshold Vcc-Hysteresis Enable-Start-Threshold Enable-Stop-Threshold Enable-Hysteresis Enable leakage current VCC_UVLO_Start VCC_UVLO_Stop Vcc-Hys Enable_UVLO_Start Enable_UVLO_Stop Enable_Hys Ien Vcc Rising Trip Level Vcc Falling Trip Level Supply ramping up and down Supply ramping up Supply ramping down Supply ramping up and down Enable=3.3V 4.06 3.76 0.25 1.14 0.9 0.16 4.26 3.96 0.3 1.2 1.0 0.2 4.46 4.16 0.38 1.36 1.06 0.25 18 uA V
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Electrical Specifications (continued)
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oCParameter Oscillator
Rt Voltage Frequency FS Rt=59K Rt=28.7K Rt=9.31K, Note4 Ramp Amplitude Ramp Offset Min Pulse Width Fixed Off Time Max Duty Cycle Dmax Vramp Ramp (os) Dmin(ctrl) Note4 Note4 Note4 Note4 Fs=250kHz 92 0.665 225 450 1350 0.7 250 500 1500 1.8 0.6 50 130 200 ns % 0.735 275 550 1650 Vp-p V kHz V
Symbol
Test Condition
Min
TYP
MAX
Units
Error Amplifier
Input Offset Voltage Input Bias Current Input Bias Current Sink Current Source Current Slew Rate Gain-Bandwidth Product DC Gain Maximum Voltage Minimum Voltage Common Mode Voltage Vos IFb(E/A) IVp(E/A) Isink(E/A) Isource(E/A) SR GBWP Gain Vmax(E/A) Vmin(E/A) Note4 0 Note4 Note4 Note4 Vcc=4.5V Vfb-Vseq, Vseq=0.8V -10 -1 -1 0.40 8 7 20 100 3.4 0.85 10 12 30 110 3.5 120 0 +10 +1 +1 1.2 13 20 40 120 3.7 220 1 mA V/s MHz dB V mV V mV A
Soft Start/SD
Soft Start Current Soft Start Clamp Voltage Shutdown Output Threshold ISS Vss(clamp) SD Source 14 2.7 20 3.0 26 3.3 0.3 V A
Over Current Protection
OCSET Current IOCSET Fs=250kHz Fs=500kHz Fs=1500kHz OC Comp Offset Voltage SS off time VOFFSET SS_Hiccup Note4 20.8 43 136 -10 23.6 48.8 154 0 4096 26.4 54.6 172 +10 mV Cycles A
Bootstrap Diode
Forward Voltage I(Boot)=30mA 180 260 470 mV
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Electrical Specifications (continued)
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oCParameter Thermal Shutdown
Thermal Shutdown Hysteresis Note4 Note4 140 20
o
SYM
Test Condition
Min
TYP
MAX
Units
C
Power Good
Power Good upper Threshold Delay Comparator Threshold Delay Comparator Hysteresis PGood Voltage Low PGood Comparator Delay Leakage Current VPG+ PG(Delay) Delay(hys) PG(voltage) PG(Delay) Ileakage SW=0V, Enable=0V Isw SW=0V,Enable=high,SS=3V,Seq=0V, Note4 3 40 A Fb Rising Relative to charge voltage, SS rising Note4 IPGood=-5mA 256/Fs 0 10 83 2 260 88 2.1 300 93 2.3 340 0.5 %Vref V mV V s A
Switch Node
SW Bias Current
Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production.
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TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz
Icc(Stan db y) 240.0
19.0 18.0 Icc(Dyn )
220.0
[m A]
[u A ]
17.0 16.0 15.0
200.0
180.0 -40 -20 0 20 40 60 80 100 120 T e m p [o C]
-40
-20
0
20
40
60
80
100
120
T e m p [o C ]
V fb 701.0 700.5 700.0 699.5 699.0 698.5 698.0 697.5 697.0 696.5 696.0 -40 -20 0 20 40 60 80 100 120 T e m p [oC]
ISS
24.0 23.5 23.0
[m V]
[u A ]
22.5 22.0 21.5 21.0 - 40 - 20 0 20 40 Temp[ oC] 60 80 100 120
FREQUENCY 510.0 508.0 506.0 504.0 502.0 500.0 498.0 496.0 494.0 492.0 490.0 -40 -20 0 20 40 60 80 100 120 T e m p[o C]
50.6 50.4 50.2 50.0 49.8 49.6 49.4 49.2 49.0 48.8 48.6 -40 -20 0
IOCSET (500k Hz )
[kHz ]
[u A]
20
40
60
80
100
120
Te m p [oC]
V cc(UV LO) Star t 4.36 4.34 4.32 4.30 [V] 4.26 4.24 4.22 4.20 -40 -20 0 20 40 60 80 100 120 Te m p[o C]
V cc(UV L O) Stop 4.00 3.99 3.98 [V] 3.97 3.96 3.95 3.94 -40 -20 0 20 40 60 80 100 120 Te m p [oC]
4.28
Enab le (UV LO) Star t 1.240 1.235 1.230 1.225 [V] 1.215 1.210 1.205 1.200 -40 -20 0 20 40 60 80 100 120 Te m p [oC]
En able (UV L O) Stop 1.030 1.025 1.020 [V] 1.015 1.010 1.005 1.000 -40 -20 0 20 40 60 80 100 120 T e m p[o C]
1.220
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Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Io=1A-12A, Fs=600kHz, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement.
Vout (V) 1 1.2 1.5 1.8 3.3 5 L (uH) 0.22 0.36 0.56 0.6 1 1 P/N PA1320-221NL ETQP4LR36WFC ETQP4LR56WFC MPL104-0R6 MPL105-1R0 MPL105-1R0 DCR (m) 0.48 1.1 1.56 1.7 2.5 2.5
98 96 94 92 90 Efficien cy (%) 88 86 84 82 80 78 76 74 72 1 2 3 4 5 6 7 8 9 10 11 12 Lo ad Cu rre n t (A)
1V out
1.2V out
1.5V out
1.8V out
3.3V out
5V out
3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1 2 3 4 5 6 7 8 9 10 11 12
Loa d Curre nt (A)
P ower Loss (W)
1V out
1.2V out
1.5V out
1.8V out
3.3V out
5V out
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Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Io=1A-12A, Fs=600kHz, Room Temperature, No Air Flow For all the output voltages, L=0.3uH (DCR=0.29 m, P/N: 59PR9874N)
97 95 93 91 89 87 85 83 81 79 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.9Vout 1.8Vout 8.0 9.0 1.0Vout 2.5Vout 10.0 11.0 1.1Vout 3.3Vout 12.0
Efficiency (%)
Load Current (A)
0.7Vout 1.2Vout 0.75Vout 1.5Vout
2.5 2.3 2.1 1.9
Power Loss (W)
1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 1 2 3 4 5 6 7 8 9 10 11 12
Load Current (A)
0.7Vout 1.2Vout 0.75Vout 1.5Vout 0.9Vout 1.8Vout 1.0Vout 2.5Vout 1.1Vout 3.3Vout
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Circuit Description
THEORY OF OPERATION
Introduction The IR3840 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3840 provides precisely regulated output voltage programmed via two external resistors from 0.7V to 0.9*Vin. The IR3840 operates with an external bias supply from 4.5V to 5.5V, allowing an extended operating input voltage range from 1.5V to 16V. The device utilizes the on-resistance of the low side MOSFET as current sense element, this method enhances the converter's efficiency and reduces cost by eliminating the need for external current sense resistor. IR3840 includes two low Rds(on) MOSFETs using IR's HEXFET technology. These are specifically designed for high efficiency applications. Under-Voltage Lockout and POR The under-voltage lockout circuit monitors the input supply Vcc and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted the soft start sequence starts (see soft start section). Enable The Enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3840 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. 06/18/09 If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3840 does not turn on until the bus voltage reaches the desired level. Only after the bus voltage reaches or exceeds this level will the voltage at Enable pin exceed its threshold, thus enabling the IR3840. Therefore, in addition to being a logic input pin to enable the IR3840, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage Vin. This is desirable particularly for high output voltage applications, where we might want the IR3840 to be disabled at least until Vin exceeds the desired output voltage level.
Fig. 3a. Normal Start up, Device turns on when the Bus voltage reaches 10.2V Figure 3b. shows the recommended start-up sequence for the non-sequenced operation of IR3840, when Enable is used as a logic input.
Fig. 3b. Recommended startup sequence, Non-Sequenced operation
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IR3840MPBF
Figure 3c. shows the recommended startup sequence for sequenced operation of IR3840 with Enable used as logic input.
Fig. 5. Pre-Bias startup pulses Soft-Start The IR3840 has a programmable soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal current source (typically 20uA) charges the external capacitor Css linearly from 0V to 3V. Figure 6 shows the waveforms during the soft start. The start up time can be estimated by:
Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3840 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure 4 shows a typical Pre-Bias condition at start up. The synchronous MOSFET always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. The number of these startup pulses for the synchronous MOSFET is internally programmed. Figure 5 shows a series of 32, 16, 8 startup pulses.
Tstart =
(1.4 - 0.7) * CSS
20A
- - - - - - - - - - - - - - - - - - - - (1)
During the soft start the OCP is enabled to protect the device for any short circuit and over current condition.
Fig. 6. Theoretical operation waveforms during soft-start
Fig. 4. Pre-Bias startup 06/18/09 12
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Operating Frequency The switching frequency can be programmed between 250kHz - 1500kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. Table 1. Switching Frequency and IOCSet vs. External Resistor (Rt)
I OCSet (A ) = 1400 .......... .......... ...............( 2) R t (k)
Table 1. shows IOCSet at different switching frequencies. The internal current source develops a voltage across ROCSet. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results in a voltage at OCSet which is given by:
Rt (k) 47.5 35.7 28.7 23.7 20.5 17.8 15.8 14.3 12.7 11.5 10.7 9.76 9.31
Fs (kHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
Iocset (A) 29.4 39.2 48.7 59.07 68.2 78.6 88.6 97.9 110.2 121.7 130.8 143.4 150.3
VOCSet = ( IOCSet ROCSet ) - ( RDS(on) I L ) .......... .(3)
Fig. 7. Connection of over current sensing resistor An over current is detected if the OCSet pin goes below ground. Hence, at the current limit threshold, VOCset=0. Then, for a current limit setting ILimit, ROCSet is calculated as follows:
ROCSet = R
DS (on)
Shutdown The IR3840 can be shutdown by pulling the Enable pin below its 1 V threshold. This will tristate both, the high side driver as well as the low side driver. Alternatively, the output can be shutdown by pulling the soft-start pin below 0.3V. In shutdown by this method, the high side driver is turned off, and the low side driver is turned on. Thus, in this method, the output voltage can be actively discharged through the synchronous FET. Normal operation is resumed by cycling the voltage at the Soft Start pin. Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter's efficiency and reduces cost by eliminating a current sense resistor. As shown in figure 7, an external resistor (ROCSet) is connected between OCSet pin and the switch node (SW) which sets the current limit set point. An internal current source sources current (IOCSet ) out of the OCSet pin. This current is a function of the switching frequency and hence, of Rt. 06/18/09
* I Limit
IOCSet
.......... .......... (4) ....
An overcurrent detection trips the OCP comparator, latches OCP signal and cycles the soft start function in hiccup mode. The hiccup is performed by shorting the soft-start capacitor to ground and counting the number of switching cycles. The Soft Start pin is held low until 4096 cycles have been completed. The OCP signal resets and the converter recovers. After every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. The OCP circuit starts sampling current typically 160 ns after the low gate drive rises to about 3V. This delay functions to filter out switching noise.
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Thermal Shutdown Temperature sensing is provided inside IR3840. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. Output Voltage Sequencing The IR3840 can accommodate user programmable sequencing options using Seq, Enable and Power Good pins.
1.5V Enable Vcc PGood PGood Seq Rt
Vin
Boot Vo(master) SW
OCSet Fb
RA
RB PGnd Comp
SS/ SD
Gnd
4.5V Enable Vo(master) PGood Vcc
Vin
Boot Vo(slave) SW
Vo1
RE RF
PGood Seq
OCSet Fb
RC
Vo2
Rt Comp
RD Gnd PGnd
SS/ SD
Simultaneous Powerup
Fig. 8a. Simultaneous Power-up of the slave with respect to the master. Through these pins, voltage sequencing such as simultaneous and sequential can be implemented. Figure 8. shows simultaneous sequencing configurations. In simultaneous power-up, the voltage at the Seq pin of the slave reaches 0.7V before the Fb pin of the master. For RE/RF =RC/RD, therefore, the output voltage of the slave follows that of the master until the voltage at the Seq pin of the slave reaches 0.7 V. After the voltage at the Seq pin of the slave exceeds 0.85V, the internal 0.7V reference of the slave dictates its output voltage.
Fig. 8b. Application Circuit for Simultaneous Sequencing Power Good Output The IC continually monitors the output voltage via Feedback (Fb pin). The feedback voltage is compared to a fixed voltage. As soon as the Fb voltage reaches 0.88*Vref, the Power Good signal flags. This pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Fig 9. shows the timing diagram for the PGood function.
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TIMING DIAGRAM OF PGOOD FUNCTION
Fig.9a IR3840 Non-Sequenced Operation (Seq=Vcc)
Fig.9b IR3840 Sequencing Operation
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Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3840, the typical minimum on-time is specified as 50 ns. Any design or application using the IR3840 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple.
t on = D Fs
Max D uty C ycle (% )
Maximum Duty Ratio Considerations
A fixed off-time of 200 ns maximum is specified for the IR3840. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3840 can operate. To allow some margin, the maximum operating duty ratio in any application using the IR3840 should still accommodate about 250 ns off-time. Fig 10. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time.
M a x Duty Cycle
Vout = Vin x Fs
In any application that uses the IR3840, the following condition must be satisfied:
t on (min) t on t on (min) Vout Vin x Fs Vout
95 90 85 80 75 70 65 60 55 250 450 650 850 1050 1250 1450 1650 S w itching Frequency (kH z )
t on(min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.7 V. Therefore, for Vout(min) = 0.7 V,
Vin x Fs Vout (min) t on(min) 0.7 V = 7 x 10 6 V/s 100 ns
Vin x Fs
Fig. 10. Maximum duty cycle v/s switching frequency.
Vin x Fs
Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 440 kHz. Conversely, for operation at the maximum recommended operating frequency 1.65 MHz and minimum output voltage, any voltage above 4.2 V may not be stepped down without pulseskipping.
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Application Information Design Example:
The following example is a typical application for IR3840. The application circuit is shown on page 23.
Vin = 12 V ( 13.2V max) Vo = 1.8 V I o = 12 A Vo 54mV Fs = 600 kHz
When an external resistor divider is connected to the output as shown in figure 11. Equation (5) can be rewritten as:
V R9 = R8 ref V -V o ref .......... .......... .......... (8) ....
For the calculated values of R8 feedback compensation section.
and R9 see
VOUT
IR3840 IR3624
Fb R9 R8
Enabling the IR3840
As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage.
Fig. 11. Typical application of the IR3840 for programming the output voltage
Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. From (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using:
C SS (F) = Tstart ( ms ) x 0.02857 .......... (9)
V in
IR3840
Enable
R1 R2
For a typical Enable threshold of VEN = 1.2 V
Vin(min) * R2 = VEN = 1.2 .......... (5) R1 + R 2
Where Tstart is the desired start-up time (ms). For a start-up time of 3.5ms, the soft-start capacitor will be 0.099F. Choose a 0.1F ceramic capacitor.
Bootstrap Capacitor Selection
VEN R 2 = R1 .......... (6) Vin( min ) - VEN
For a Vin (min)=10.2V, R1=4.99K and R2=750 ohm is a good choice.
Programming the frequency For Fs = 600 kHz, select Rt = 23.7 k, using Table. 1. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.7V. The divider is ratioed to provide 0.7V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation:
To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected the source of the Control FET . This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C6). The operation of the circuit is as follows: When the lower MOSFET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C6 is approximately given as
Vc Vcc - VD .......... .......... ...... (10)
R .......... .......... .....(7) Vo = Vref 1 + 8 .......... R 9
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When the upper MOSFET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C6 is appropriately chosen,
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IR3840MPBF
the voltage Vc across C6 remains approximately unchanged and the voltage at the Boot pin becomes
VBoot Vin + Vcc - VD ........................................ (11)
Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (i ). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation:
Vin - Vo = L i 1 ; t = D t Fs .......... .......... .......... . (14) Vo L = (Vin - Vo ) Vin i * Fs
Fig. 12. Bootstrap circuit to generate Vc voltage
A bootstrap capacitor of value 0.1uF is suitable for most applications.
Input Capacitor Selection The ripple current generated during the on time of the upper MOSFET should be provided by the input capacitor. The RMS value of this ripple is expressed by:
Where: Vin = Maximum input voltage
Vo = Output Voltage i = Inductor ripple current F s = Switching frequency t = Turn on time D = Duty cycle
IRMS = Io D (1 - D) .......... .......... ....(12)
Vo .......... .......... .......... (13) .. Vin Where: D=
If i 35%(Io), then the output inductor is calculated to be 0.607H. Select L=0.6 H. The MPL104-0R6 from Delta provides a compact, low profile inductor suitable for this application.
D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For Io=12A and D = 0.15, the IRMS = 4.28A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF 16V ceramic capacitors ECJ-3YX1C106K from Panasonic. In addition to these, although not mandatory, a 1X330uF, 25V SMD capacitor EEV-FK1E331P may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. .
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Output Capacitor Selection
The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as
Vo = Vo( ESR ) + Vo( ESL ) + Vo(C ) Vo( ESR ) = I L * ESR V - Vo Vo( ESL ) = in * ESL L Vo(C ) = Vo = Output I L = Inductor I L 8 * C o * Fs voltage ripple ripple current .......... .......... ..... (15)
The output LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 13). The resonant frequency of the LC filter is expressed as follows: FLC =
1 2 Lo Co
................................ (16)
Figure 13 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable.
Gain 0 dB -40dB/decade
Phase 00
-1800 FLC Frequency
Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3840 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Six of the Panasonic ECJ2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is a good choice.
FLC Frequency
Fig. 13. Gain and Phase of LC filter The IR3840 uses a voltage-type error amplifier with high-gain (110dB) and wide-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Fig. 14. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor's ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor is expressed as follows:
Feedback Compensation
The IR3840 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0 dB crossing frequency and adequate phase margin (greater than 45o).
FESR =
1 .......... .......... ....... (17) 2 *ESR*C o
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Z IN VOUT R3 R8 Fb R9
Gain(dB)
C POLE C4 Zf
Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 = Feedback Resistor To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
Fz = 75%FLC Fz = 0.75* 1 2 Lo * Co .......... .......... .......... (22) .......
E/A
Comp
Ve
VREF
H(s) dB
FZ
F
POLE
Frequency
Fig. 14. Type II compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by:
Ve 1 + sR3C4 Z = H(s) = - f = - .....(18) ZIN sR8C4 Vo
Use equations (20), (21) and (22) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by:
FP = 1 .......... .......... .......... ...(23) C4 * CPOLE 2 * R3 * C4 + CPOLE
The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by:
H(s) = R3 ......... .......... .......... .........(19) R8
The pole sets to one half of the switching frequency which results in the capacitor CPOLE:
CPOLE =
1
*R3*Fs -
1 C4
1 .......... .......... 24) ..( *R3*Fs
1 Fz = .......... .......... ........(20) 2 * R3 * C4
First select the desired zero-crossover frequency (Fo):
For a general solution for unconditional stability for any type of output capacitors, and a wide range of ESR values, we should implement local feedback with a type III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 15. Again, the transfer function is given by:
Ve Z = H(s) = - f Vo ZIN
) Fo > FESR and Fo (1/5 ~ 1/10 * Fs
Use the following equation to calculate R3:
R3 = Vosc * Fo * FESR * R8
2 Vin * FLC
.......... .......... (21) .......
By replacing Zin and Zf according to figure 15, the transfer function can be expressed as:
- H(s) = (1 + sR3C4 )[1 + sC7 (R8 + R10 )] C * C3 sR8 (C4 + C3 )1 + sR3 4 C + C (1 + sR10C7 ) 3 4 ....(25)
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ZIN C7 R10 R8 Fb R9
Gain(dB)
VOUT R3
C3 C4 Zf
Compensator Type
FESR vs Fo
Output Capacitor Electrolytic Tantalum Tantalum Ceramic
Type II
FLCE/A
Comp
Ve
Type III
FLCVREF
H(s) dB
The higher the crossover frequency, the potentially faster the load transient response. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency is selected such that
FZ1
FZ2
FP2
FP3
Frequency
) F (1/5 ~ 1/10 * Fs o
The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. For this design we have: Vin=12V Vo=1.8V Vosc=1.8V Vref=0.7V Lo=0.6uH Co=6x22uF, ESR=3mOhm each It must be noted here that the value of the capacitance used in the compensator design must be the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 12uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer's datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (16) to compute the small signal Co. These result to: FLC=24.2 kHz FESR=4.4 MHz Fs/2=300 kHz Select crossover frequency Fo=100 kHz Since FLCFig.15. Type III Compensation network and its asymptotic gain plot The compensation network has three poles and two zeros and they are expressed as follows:
FP1 = 0 .......... .......... .......... .......... .......... .......... ......(26) FP 2 = FP3 = 1 .......... .......... .......... .......... .......(27) 2 * R10 * C7 1 1 .......... (28) ..... 2 * R3 * C3
FZ1
C * C3 2 * R3 4 C + C 3 4 1 = .......... .......... .......... .......... .....(29) 2 * R3 * C4
FZ 2 =
1 1 .......... (30) 2 * C7 * (R8 + R10 ) 2 * C7 * R8
Cross over frequency is expressed as:
Fo = R3 * C7 *
Vin 1 * .......... .......... .......... (31) .. Vosc 2 * Lo * Co
Based on the frequency of the zero generated by the output capacitor and its ESR, relative to crossover frequency, the compensation type can be different. The table below shows the compensation types for relative locations of the crossover frequency.
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Detailed calculation of compensation TypeIII
Desired Phase Margin = 70o FZ2 = Fo 1 - sin = 17.63kHz 1 + sin 1 + sin = 567.1kHz 1 - sin
FP2 = Fo
Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (ROCSET) from the SW pin to the OCSet pin. The resistor can be calculated by using equation (4). This resistor ROCSET must be placed close to the IC. The RDS(on) has a positive temperature coefficient and it should be considered for the worst case operation.
Select FZ1 = 0.5 * FZ2 = 8.82 kHz and : FP3 = 0.5* Fs = 300 kHz Select C7 = 2.2nF : Calculate R3, C3 and C4 : R3 = 2 * Fo * Lo * Co * Vosc ;R3 = 1.85 k C7 * Vin
ISET = IL (critical = )
ROCSet IOCSet .......... .......... (32) ... RDS(on)
RDS(on) = 5.9 m *1.5 = 8.85 m ISET Io(LIM) = 12 A * 1.5 = 18 A (50% over nominal output current ) IOCSet = 59.07 A (at Fs = 600kHz) ROCSet = 2.696 k Select R7 = 2.8 k
Select R3 = 1.87 k : C4 = 1 ; C4 = 9.65 nF, Select C4 = 10 nF : 2 * FZ1 * R 3 1 ; C3 = 283.7pF Select C3 = 220 pF , : 2 * FP3 * R3
Setting the Power Good Threshold Power Good threshold is internally set at 88% of Vref. When the voltage at the FB pin exceeds the threshold, PGood is asserted.
C3 =
The PGood is an open drain output. Hence, it is necessary to use a pull up resistor RPG from PGood pin to Vcc. The value of the pull-up resistor must be chosen such as to limit the current flowing into the PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 4.7k.
Calculate R10, R8 and R9 : R10 = 1 ; R10 = 128 , Select R10 = 130 : 2 * C7 * FP2 1 - R10; R8 = 3.97 k, 2 * C7 * FZ2
R8 =
Select R8 = 3.92 k : R9 = Vref * R8; R9 = 2.49 k Select R9 = 2.49 k : Vo - Vref
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Application Diagram:
Vin =12 V
R1 4.99 K
Cin= 4 X 10 uF + 330 uF
4.5 V R2 750
Enable
CVcc RPG 4.7 K 1 uF
Vin
Boot SW
Vcc
C6 0.1 uF Lo 0.6uH R8 3.92 K
Vo
PGood PGood Seq Rt
Rt 23.7 K
IR3840
ROCSet 2.8 K
OCSet Fb
C4 10 nF
C7 2.2nF R10 130 Co=6X22uF
R3 1.87 K
R9 2.49 K
SS/ SD
CSS 0.1 uF
Gnd
PGnd
Comp
C3 220 pF
Fig. 16. Application circuit diagram for a 12V to 1.8 V, 12 A Point Of Load Converter
Suggested Bill of Materials for the application circuit:
Part Reference Cin Lo Co R1 R2 Rt ROCSet RPG Css R3 C3 C4 R8 R9 R10 C7 U1 Quantity 1 4 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 Value 330uF 10uF 0.6uH 22uF 4.99K 750 23.7k 4.7K 0.1uF 1.87k 220pF 10000pF 3.92K 2.49K 130 2200pF IR3840 Description SMD Elecrolytic, Fsize, 25V, 20% 1206, 16V, X7R, 20% 11.5x10x4mm, 20%, 1.7mOhm 0805, 6.3V, X5R, 20% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% 0603, 25V, X7R, 10% Thick Film, 0603,1/10W,1% 50V, 0603, NPO, 5% 0603, 50V, X7R, 10% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 0603, 50V, X7R, 10% SupIRBuck PQFN 5x6mm Manufacturer Panasonic Panasonic - ECG Delta Panasonic- ECG Rohm Rohm Rohm Rohm Rohm Panasonic - ECG Rohm Panasonic- ECG Panasonic - ECG Rohm Rohm Panasonic - ECG Panasonic - ECG International Rectifier Part Number EEV-FK1E331P ECJ-3YX1C106K MPL104-0R6 ECJ-2FB0J226ML MCR03EZPFX4991 MCR03EZPFX7500 MCR03EZPFX2372 MCR03EZPFX2801 MCR03EZPFX4701 ECJ-1VB1E104K MCR03EZPFX1871 ECJ-1VC1H221J ECJ-1VB1H103K MCR03EZPFX3921 MCR03EZPFX2491 ERJ-3EKF1300V ECJ-1VB1H222K IR3840MPBF
1 2.8k
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-12A, Room Temperature, No Air Flow
Fig. 17. Start up at 12A Load Ch1:Vo, Ch2:Vin, Ch3:Vss, Ch4:Enable
Fig. 18. Start up at 12A Load, Ch1:Vo, Ch2:Vin, Ch3:Vss, Ch4:VPGood
Fig. 19. Start up with 1.62V Pre Bias, 0A Load, Ch1:Vo, Ch3:VSS
Fig. 20. Output Voltage Ripple, 12A load Ch2: Vout
Fig. 21. Inductor node at 12A load Ch3:LX
Fig. 22. Short (Hiccup) Recovery Ch1:Vout , Ch3:VSS
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-12A, Room Temperature, No Air Flow
Fig. 23. Transient Response, 6A to 12A step Ch1:Vout, Ch4:Iout
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=12A, Room Temperature, No Air Flow
Fig. 24. Bode Plot at 12A load shows a bandwidth of 109 kHz and phase margin of 51 degrees
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Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make all the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3840 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3840. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins.
AGnd
The connection between the OCSet resistor and the Sw pin should not share any trace with the connection between the bootstrap capacitor and the Sw pin. Instead, it is recommended to use a Kelvin connection of the trace from the OCSet resistor and the trace from the bootstrap Vin capacitor at the Sw pin. PGnd In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not Vout interfere with the more sensitive analog control AGnd function. These two grounds must be connected together on the PC board layout at a single point. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 25 illustrates the implementation of the layout guidelines outlined above, on the IRDC3840 4 layer demoboard.
Vin
PGnd
Vout
Compensation parts should be placed as close as possible to the Comp pin.
PGnd Vin
Vin PGnd
Enough copper & minimum length ground path between Input and Output
All bypass caps should be placed as close as possible to their connecting pins.
Resistors Rt and Rocset should be placed as close as possible to their pins.
AGnd
Vout
AGnd
Vout
Fig. 25a. IRDC3840 demoboard layout considerations - Top Layer
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Feedback trace should be kept away form noise sources
PGnd
Fig. 25b. IRDC3840 demoboard layout considerations - Bottom Layer
Analog Ground plane Power Vin Ground Plane
Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources.
AGnd
Fig. 25c. IRDC3840 demoboard layout considerations - Mid Layer 1
Use separate traces for connecting Boot cap and Rocset to the switch node and with the minimum length traces. Avoid big loops.
Fig. 25d. IRDC3840 demoboard layout considerations - Mid Layer 2
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PCB Metal and Components Placement
Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper.
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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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Stencil Design
* The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
*
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BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 01/09 06/18/09 32

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